The present invention relates to semiconductor technologies, and more particularly to a layout structure, a semiconductor device and an electronic apparatus.
In semiconductor technology field, laterally diffused metal oxide semiconductor (LDMOS) has apparent advantages over transistors in key device characteristics (such as gain, linearity, switching performance, thermal dissipation performance and stage number reduction, etc.), and can be easily made compatible with complementary metal oxide semiconductor (CMOS) technology, and thus is widely used in fields such as radio frequency circuits.
In current technology, a conventional LDMOS layout shown in FIG. 1A includes a source 101, a drain 102 and a gate 103. Among them, source 101, drain 102 and gate 103 are all strip-shaped structures. The overlapping area of gate 103 and source 101 defines the channel width of the device, and thus determines the current density per unit area of the device. In an existing LDMOS layout, source 101 and gate 103 are strip-shaped, which limits the overlapping area between them, and therefore, in certain practical applications, it is difficult for such LDMOS layout to meet the requirements of large current density per unit area and small LDMOS area (i.e., size of the device).
In addition, in a layout design of a semiconductor device including at least two adjacent LDMOS devices, if the LDMOS layout uses a structure shown in FIG. 1A, the layout structure of the semiconductor device is generally as shown in FIG. 1B, which includes source 101, drain 102, gate 103, a body electrode 104, and contact holes (CTs) 105, wherein source 101, drain 102 and gate 103 are all strip-shaped, and adjacent LDMOS devices share a drain. In such layout structure, because source 101, drain 102 and gate 103 are all strip-shaped, in order to achieve body pickup, two to three rows of contact holes 105 are typically disposed in a neighboring region between two adjacent LDMOS devices. FIG. 1B illustrates an embodiment where three rows of contact holes 105 are disposed in a neighboring region between two adjacent LDMOS devices, wherein a row of contact holes is disposed on the source of each of the two LDMOS devices and a row of contact holes is disposed on the body electrode at a neighboring location of the adjacent LDMOS devices. It can be seen that, because such layout structure provides 2 to 3 rows of contact holes in the neighboring region between two adjacent LDMOS devices, a significant layout area may be wasted, which goes against reducing layout area.
Thus, existing LDMOS layout has difficulties in increasing the current density per unit area and reducing the area of the LDMOS, and a semiconductor device layout structure including a plurality of LDMOS layouts would occupy a large layout area due to the presence of 2 to 3 rows of LDMOS contact holes at a neighboring region between adjacent LDMOS devices. Therefore, in order to solve the above technical problems, it is desirable to provide a new layout structure.